In placement and routing (P&R) technologies for IC design, use of metal 1 (M1) back-to-back (B2B) routes improves routing efficiency, chip scaling, and circuit performance. FIG. 1 illustrates an exemplary P&R layout of a M1 layer. As shown, cells 101a and 101b have edge pins 103a and 103b connected by M1 B2B route 105. Additionally, the M1 layer includes a power rail 107 (e.g., Vss) and ground rail 109 (e.g., Vdd). As illustrated in FIG. 1, M1 B2B routes 105 improve routing efficiency, chip scaling, and circuit performance, by, for instance, enabling different cells (e.g., 101a and 101b) to be connected via edge pins (e.g., 103a and 103b) within the M1 layer. That is, M1 B2B routes 105 remove the need to connect edge pins (e.g., 103a, 103b) using another layer (e.g., metal 2 layer).
However, features (e.g., routes, edge pins, etc.) and pitches (e.g., spacing between features) of IC designs continue to decrease in size. In order to support such features and pitches, many IC designs form features utilizing DPT. FIG. 2 illustrates an exemplary DPT process. As shown, an overall route pattern 201 is generated from a partial route pattern 201a formed by a first mask (and/or color space) and a partial route pattern 201b formed by a second mask (and/or second color space). By using two separate masks (and/or color spaces), the pitch 203 between features using DPT may be less than (e.g., half) a pitch using a single mask, such as pitch 203a and pitch 203b. IC designs utilizing DPT, however, require zero odd cycles for the designs to be decomposable by the separate masks. Additionally, some odd cycles may be removed using a stitch (e.g., a continuous metal geometry/polygon decomposed into two masks). Stitch generation, however, utilizes complicated stitching color (DPT) rules, particularly in the M1 layer. Thus, a layout decomposition tool, rather than traditional IC P&R technologies, utilizes the stitching color rules to generate stitches.
As such, traditional P&R technologies utilizing DPT either require compliance with color rules (i.e., without the stitching color rules), as described further with respect to FIG. 3, or ignore the affect of DPT, as described further with respect to FIG. 4.
Traditional P&R routing technologies utilizing color rules guarantee M1 decomposability, but generate IC designs having reduced routing efficiency. Adverting to FIG. 3, a target pattern 301 for the M1 layer is composed of edge pins 303 and 305 connected together by a target M1 B2B route 307. A first mask having a critical dimension (CD) 309 is designated to decompose a partial pattern 301a having edge pin 303. Similarly, a second mask having the CD 309 is designated to decompose a partial pattern 301b having edge pin 305. Traditional P&R routing technologies are unaware of stitching color rules and thus generate a route (not shown) connecting edge pins 303 and 305 in another layer (e.g., metal layer 2) rather than generating the M1 B2B route 307. As such, traditional P&R technologies using color rules overly restrict the generation of M1 B2B routes resulting in reduced routing efficiency, chip scaling, and circuit performance of a resulting IC design. Additionally, color rules in the M1 layer are particularly difficult to implement because M1 layer geometries of standard cells frequently contain two-dimensional shapes that require complicated color rules.
Traditional P&R technologies ignoring the effect of DPT rules (i.e., colorless) may allow for additional M1 B2B routes, but do not guarantee M1 decomposability. Adverting to FIG. 4, a target pattern 401 for the M1 layer includes edge pins 403, 405, and 407, with edge pins 403 and 407 connected together by a target M1 B2B route 409. Similar to FIG. 3, the M1 B2B route 409 cannot be decomposed using a single mask. A first mask is designated to decompose a partial pattern 401a having edge pin 403 and a part 409a of M1 B2B route 409. Similarly, a second mask is designated to decompose a partial pattern 401b having edge pins and 405 and 407, and a part 409b of M1 B2B route 409. However, the second mask cannot decompose partial pattern 401b due to a tip-to-tip conflict between edge pin 405 and a part 409b of M1 B2B route 409. Specifically, tip-to-tip distance 411 between edge pin 405 and the part 409b of M1 B2B route 409 is less than a CD for the second mask, resulting in an odd (e.g., three) number of masks being required to decompose the target pattern 401. As such, the M1 B2B route 409 is not decomposable in the masks separately or in combination. Thus, traditional colorless P&R technologies may result in M1 layers that cannot be decomposed utilizing DPT.
A need therefore exists for a methodology enabling M1 B2B routes that maintain high routing efficiency and guarantee M1 decomposability of a target pattern, and a resulting IC.